Embodiments of the invention generally relate to high-k dielectric and/or metal gate technology. More specifically, embodiments of the invention are directed to methods of depositing metal gate electrodes.
Microelectronic devices are fabricated on a semiconductor substrate as integrated circuits in which various conductive layers are interconnected with one another to permit electronic signals to propagate within the device. An example of such a device is a complementary metal-oxide-semiconductor (CMOS) field effect transistor (FET) or MOSFET.
Over the past decades, the MOSFET has continually been scaled down in size and modern integrated circuits are incorporating MOSFETs with channel lengths of less than 0.1 micron. Devices with a 65 nm feature size (with the channel being even shorter) are currently in production. The decrease in feature size has resulted in certain challenges because small MOSFETs exhibit higher leakage currents, and lower output resistance than larger devices. Still, smaller MOSFETs are desirable for several reasons. The main reason to make transistors smaller is to pack more and more devices in a given chip area, reducing the price per chip. Additionally, the reduction in transistor dimension can help increase the speed.
Because of small MOSFET geometries, the voltage that can be applied to the gate must be reduced to maintain reliability. To maintain performance, the threshold voltage of the MOSFET has to be reduced as well. As threshold voltage is reduced, the transistor cannot be switched from complete turn-off to complete turn-on with the limited voltage swing available. Subthreshold leakage, which was ignored in the past, now can have a significant impact on device performance.
A gate electrode is part of an integrated circuit. For example, a CMOS transistor comprises a gate structure disposed between source and drain regions that are formed in the semiconductor substrate. The gate structure generally comprises a gate electrode and a gate dielectric. The gate electrode is disposed over the gate dielectric to control a flow of charge carriers in a channel region that is formed between drain and source regions beneath the gate dielectric. The gate dielectric typically comprises a thin material layer having a dielectric constant of about 4.0 or greater (for example, gate oxides such as silicon dioxide (SiO2), silicon oxynitride (SiON), and the like). As the gate length of silicon CMOS devices is scaled to less than 100 nm, new high dielectric constant (K) materials will likely replace silicon oxide. In addition, metal gates will likely replace polycrystalline silicon (polysilicon) gates. For example, in some CMOS transistors, the gate electrode may be formed from at least one of a metal (e.g., titanium (Ti), tantalum (Ta), tungsten (W), and the like) and metal-containing conductive compound (e.g., titanium nitride (TiN), tantalum nitride (TaN)). Replacement of polysilicon as a traditional material of the gate electrode with metals and metal-containing compounds reduces undesired voltage drops associated with the polysilicon depletion effect, as well as increases drive current performance and the operational speed of the CMOS transistor.
Currently, ALD TiN has been used for two different steps in the metal gate process: high-k cap layer and/or PMOS work function metal. Many logic/foundry manufacturers utilize a furnace-based process using TiCl4 and NH3 as the precursors. However, the film produced with this process can have high oxygen content and therefore may not be ideal for future scalability (oxygen can increase the electrical thickness). There is therefore a need for improved films which do not exhibit these types of problems.